A memory cell in an integrated circuit (IC) may include a transfer device such as a transistor and an associated capacitor. The transistor is a solid state semiconductor device which can be used for amplification, switching, voltage stabilization, signal modulation and many other functions. Generally, a transistor has three terminals, and a voltage applied to a specific one of the terminals controls current flowing between the other two terminals. One type of transistor is known as the field effect transistor (FET). The capacitor, which is typically formed in a portion of a trench, consists of a pair of conductive plates (electrodes), which are separated from each other by a node dielectric material. Information or data is stored in the memory cell in the form of charge accumulated on the capacitor. Because capacitors leak charge (generally, a capacitor is only useful for temporarily storing an electrical charge), the information (data) eventually fades unless the capacitor charge is refreshed (read, and re-written) periodically, such as every 64 ms (milliseconds).
DRAM (eDRAM)                Generally, the DRAM cells discussed herein comprise a capacitor formed in a deep trench (DT) in a substrate, and an “access transistor” formed on the surface of the substrate adjacent and atop the capacitor. The capacitor (“DT capacitor”) generally comprises a first conductive electrode called the “buried plate” which is a heavily doped region of the substrate surrounding the trench, a thin layer of insulating material such as an oxide lining the trench, and a second conductive electrode such as a heavily doped polycrystalline plug (or “node”) disposed within the trench. The transistor may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second electrode (node) of the capacitor.        
FIG. 1 illustrates a DRAM cell 100 of the prior art, and generally comprising an access transistor and an associated cell capacitor. The DRAM cell is generally formed (created), as follows.
Beginning with a semiconductor substrate 102, a deep trench (DT) 110 is formed, extending into the substrate 102, from a top (as viewed) surface thereof. The substrate 102 may comprise a SOI substrate having a layer 106 of silicon (SOI) on top of an insulating layer 104 which is atop the underlying silicon substrate 102. The insulating layer 104 typically comprises buried oxide (BOX). The deep trench (DT) 110 is used for forming the cell capacitor (or “DT capacitor”), as follows. The trench 110 may have a width of about 50 nm to 200 nm and a depth of 1000 nm to 10000 nm, by way of example.
The cell capacitor generally comprises a first conductor called the “buried plate” which is a heavily doped region 112 of the substrate surrounding the trench 110, a thin layer 114 of an insulating material lining the trench 110, and a second conductor 116 such as a heavily doped polycrystalline plug (or “node”, “DT poly”) disposed within the trench 110. A cell transistor (“access transistor”) 120 may comprise a FET having one of its source/drain (S/D) terminals connected to (or an extension of) the second conductor (node) of the capacitor, as follows.
The FET 120 comprises two spaced-apart diffusions 122, 124, within the surface of the substrate 102—one of which will serve as the “source” and the other of which will serve as the “drain” (D) of the transistor 120. The space between the two diffusion areas is called the “channel” (and is approximately where the legend “SOI” appears). A thin dielectric layer 126 is disposed on the substrate above the channel, and a “gate” structure (G) 128 is disposed over the dielectric layer 126, thus also atop the channel. (The dielectric under the gate is also commonly referred to as “gate oxide” or “gate dielectric”.) The gate 128 may be a portion of an elongate wordline (WL).
In modern CMOS technology, a shallow trench isolation (STI) is commonly used to isolate one (or more) transistors from other transistors, for both logic and memory. As shown in FIG. 1, a shallow trench 132 may be formed, surrounding the access transistor 120 (only one side of the transistor is shown). Note that the trench 132 extends over the DT (node) poly 116, a top portion of which is adjacent the drain (D) of the transistor 120. Therefore, the trench 132 is less deep (thinner) over the DT poly 116 and immediately adjacent the drain (D) of the transistor 120, and may be deeper (thicker) further from the drain (D) of the transistor 120 (and, as shown, over top portion of the DT poly 116 which is distal from (not immediately adjacent to) the drain (D) of the transistor 120.
The STI trench 132 may be filled with an insulating material, such as oxide (STI oxide) 134. Because of the thin/thick trench geometry which has been described, the STI oxide will exhibit a thin portion 134a where it is proximal (adjacent to) the drain (D) of the transistor 120, and a thicker portion 134b where it is distal from (not immediately adjacent to) the drain (D) of the transistor 120.
Although not shown, the deep trench (DT) may be “bottle-shaped”, such that it is wider in the substrate under the BOX, and a thinner bottleneck portion of the trench extends through the BOX (and overlying SOI, not shown). The deep trench is typically filled with poly (DT Poly, compare 116), there is a lining of insulator (compare 114), and the trench is surrounded by the buried plate (compare 112). This forms the deep trench capacitor, which is generally not limited to SOI.
FIG. 2 illustrates an SOI substrate 200 with pad films and a hard mask, according to the prior art.
The overall substrate 200 is an SOI-type substrate having a layer 206 of silicon (“SOI”) atop a buried oxide (BOX, insulator) layer 204, which is atop an underlying substrate 202 which may be a silicon substrate. The BOX layer 204 may have a thickness of 500-2500 Å (50-250 nm). The silicon (SOI) layer 206 may have a thickness of 50-200 Å (5-20 nm).
Pad films comprising a layer 208 of an oxide and a layer 210 of a nitride are disposed atop the SOI layer 206. The pad oxide layer 208 may have a thickness of 10-20 Å (1-2 nm), and the pad nitride layer 210 may have a thickness of 400-1500 Å (40-150 nm).
SOI Substrates                Silicon-on-insulator technology (SOI) typically refers to the use of a layered silicon-insulator-silicon substrate in place of a more conventional silicon substrate (Bulk Substrate) in semiconductor manufacturing, especially microelectronics. SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices. The precise thickness of the insulating layer and topmost silicon layer also vary widely with the intended application.        
SiO2-based SOI substrates (or wafers) can be produced by several methods:                SIMOX—Separation by IMplantation of OXygen—uses an oxygen ion beam implantation process followed by high temperature annealing to create a buried SiO2 layer.        Wafer Bonding—the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.        Seed methods—wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.        
Glossary                Unless otherwise noted, or as may be evident from the context of their usage, any terms, abbreviations, acronyms or scientific symbols and notations used herein are to be given their ordinary meaning in the technical discipline which the invention most nearly pertains. The following terms, abbreviations and acronyms may be used throughout the descriptions presented herein and should generally be given the following meaning unless contradicted or elaborated upon by other descriptions set forth herein. Some of the terms set forth below may be registered trademarks (™).        
ALDshort for atomic layer deposition. ALD is a gas phasechemical process used to create extremely thin coatings.The majority of ALD reactions use two chemicals, typicallycalled precursors. These precursors react with a surfaceone-at-a-time in a sequential manner. By exposing theprecursors to the growth surface repeatedly, a thin film isdeposited. ALD is a self-limiting, sequential surfacechemistry that deposits conformal thin-films of materialsonto substrates of varying compositions. ALD is similar inchemistry to chemical vapor deposition (CVD), except thatthe ALD reaction breaks the CVD reaction into twohalf-reactions, keeping the precursor materials separateduring the reaction. ALD film growth is self-limited andbased on surface reactions, which makes achieving atomicscale deposition control possible. By keeping the precursorsseparate throughout the coating process, atomic layer controlof film grown can be obtained as fine as ~0.1 angstroms permonolayer. ALD has unique advantages over other thin filmdeposition techniques, as ALD grown films are conformal,pin-hole free, and chemically bonded to the substrate. WithALD it is possible to deposit coatings perfectly uniform inthickness inside deep trenches, porous media and aroundparticles. The film thickness range is usually 1-500 nm.ALD can be used to deposit several types of thin films,including various ceramics, from conductors to insulators.anisotropicliterally, one directional. An example of an anisotropicprocess is sunbathing. Only surfaces of the body exposed to(facing in the direction of) the sun become tanned.Anisotropic means “not the same in all directions” or “notisotropic”. See isotropic.capacitorA capacitor is a two-terminal device (electrical or electroniccomponent) that can store energy in the electric fieldbetween a pair of conductive electrodes (called “plates”).The process of storing energy in the capaditor is known as“charging”, and involves electric charges of equalmagnitude, but opposite polarity, building up on each plate.CMPshort for chemical-mechanical polishing. CMP is a process,using both chemicals and abrasives, comparable to lapping(analogous to sanding), for removing material from a builtup structure. For example, after depositing and etching anumber of elements, the top surface of the resultingstructure may very uneven, needing to be smoothed (orlevelled) out, prior to performing a subsequent process step.Generally, CMP will level out the high spots, leaving arelatively smooth planar surface.CVDshort for chemical vapor deposition. CVD is a chemicalprocess used to produce high-purity, high-performance solidmaterials. The process is often used in the semiconductorindustry to produce thin films. In a typical CVD process, thewafer (substrate) is exposed to one or more volatileprecursors, which react and/or decompose on the substratesurface to produce the desired deposit. CVD is used todeposit materials in various forms, including:monocrystalline, polycrystalline, amorphous, and epitaxial.These materials include: silicon, oxide, nitride and metals,such as are commonly used in semiconductor fabrication.depositionDeposition generally refers to the process of applying amaterial over another material (or the substrate). Chemicalvapor deposition (CVD) is a common technique fordepositing materials. Other “deposition” techniques, such asfor applying resist or glass, may include “spin-on”, whichgenerally involves providing a stream of material to thesubstrate, while the substrate is spinning, resulting in arelatively thin, flat, evenly-distributed coating of thematerial on the underlying substrate.dielectricA dielectric is a non-conducting material or substance. (Adielectric is an electrical insulator.) Some dielectricscommonly used in semiconductor technology are SiO2(“oxide”) and Si3N4 (“nitride”). The insulating quality of adielectric may be characterized by “k”, the dielectricconstant. Generally, the higher the “k”, the better theinsulating quality of the dielectric. Oxide, for example, hasa k of approximately 3.9. A class of materials, referred to as“high-k” (or “high-K”) dielectrics, have a dielectric constanthigher than that of oxide (k > 3.9).dopantelement introduced into semiconductor to establish eitherp-type (acceptors) or n-type (donors) conductivity; commondopants in silicon: for p-type - boron (B), Indium (In); forn-type - phosphorous (P) arsenic (As), antimony (Sb).Dopants are of two types - “donors” and “acceptors”. N typeimplants are donors and P type are acceptors.dopingdoping is the process of introducing impurities (dopants)into the semiconductor substrate, or elements formed on thesemiconductor substrate, and is often performed with a mask(or previously-formed elements in place) so that only certainareas of the substrate will be doped. For example, doping isused to form the source and drain regions of an FET. An ionimplanter is typically employed for the actual implantation.An inert carrier gas such as nitrogen is usually used to bringin the impurity source (dopant).Usually in doping, a dopant, a dosage and an energy levelare specified and/or a resulting doping level may bespecified. A dosage may be specified in the number of atomsper cm2 and an energy level (specified in keV,kilo-electron-volts), resulting in a doping level(concentration in the substrate) of a number of atoms percm3. The number of atoms is commonly specified inexponential notation, where a number like “3E15” means 3times 10 to the 15th power, or a “3” followed by 15 zeroes(3,000,000,000,000,000). To put things in perspective, thereare about 1E23 (100,000,000,000,000,000,000,000) atomsof hydrogen and oxygen in a cubic centimeter (cm3) ofwater. An example of doping is implanting with B (boron)with a dosage of between about 1E12 and 1E13 atoms/cm2,and an energy of about 40 to 80 keV to produce a dopinglevel of between 1E17 and 1E18 atoms/cm3. (“/cm3” mayalso be written “cm−3”DRAMshort for dynamic random access memory. DRAM is a typeof random access memory that stores each bit of data in aseparate capacitor within an integrated circuit. Since realcapacitors leak charge, the information eventually fadesunless the capacitor charge is refreshed periodically.Because of this refresh requirement, it is a dynamic memoryas opposed to SRAM and other static metnory. Its advantageover SRAM is its structural simplicity: only one transistorand a capacitor are required per bit, compared to sixtransistors in SRAM. This DRAM to reach very highdensity. Like SRAM, it is in the class of volatile memorydevices, since it loses its data when the power supply isremoved.eDRAMshort for embedded DRAM. eDRAM is a capacitor-baseddynamic random access memory usually integrated on thesame die or in the same package as the main ASIC orprocessor, as opposed to external DRAM modules andtransistor-based SRAM typically used for caches.etchingetching generally refers to the removal of material from asubstrate (or structures formed on the substrate), and is oftenperformed with a mask in place so that material mayselectively be removed from certain areas of the substrate,while leaving the material unaffected. in other areas of thesubstrate. There are generally two categories of etching, (i)wet etch and (ii) dry etch. Wet etch is performed with asolvent (such as an acid) which may be chosen for its abilityto selectively dissolve a given material (such as oxide),while leaving another material (such as polysilicon)relatively intact. This ability to selectively etch givenmaterials is fundamental to many semiconductor fabricationprocesses. A wet etch will generally etch a homogeneousmaterial (e.g., oxide) isotropically, but a wet etch may alsoetch single-crystal materials (e.g. silicon wafers)anisotropically. Dry etch may be performed using a plasma.Plasma systems can operate in several modes by adjustingthe parameters of the plasma. Ordinary plasma etchingproduces energetic free radicals, neutrally charged, that reactat the surface of the wafer. Since neutral particles attack thewafer from all angles, this process is isotropic. Ion milling,or sputter etching, bombards the wafer with energetic ions ofnoble gases which approach the wafer approximately fromone direction, and therefore this process is highlyanisotropic. Reactive-ion etching (RIE) operates underconditions intermediate between sputter and plasma etchingand may be used to produce deep, narrow features, such asSTI trenches.FETshort for field effect transistor. The FET is a transistor thatrelies on an electric field to control the shape and hence theconductivity of a “channel” in a semiconductor material.FETs are sometimes used as voltage-controlled resistors.The terminals of FETs are designatedsource (S), drain (D) and gate (G).HTOA High Temperature Oxide (HTO) is typically prepared bya rapid thermal CVD process involving SiH4, Si2H6, and anoxidizer such as NO, N2O or O2.isotropicliterally, identical in all directions. An example of anisotropic process is dissolving a tablet in water. All exposedsurfaces of the tablet are uniformly acted upon. (see“anisotropic”)lithog-In lithography (or “photolithography”), a radiation sensitiveraphy“resist” coating is formed over one or more layers which areto be treated in some manner, such as to be selectively dopedand/or to have a pattern transferred thereto. The resist, whichis sometimes referred to as a photoresist, is itself firstpatterned by exposing it to radiation, where the radiation(selectively) passes through an intervening mask or templatecontaining the pattern. As a result, the exposed or unexposedareas of the resist coating become more or less soluble,depending on the type of photoresist used. A developer isthen used to remove the more soluble areas of the resistleaving a patterned resist. The pattered resist can then serveas a mask for the underlying layers which can then beselectively treated, such as to receive dopants and/or toundergo etching, for example.maskThe term “mask” may be given to a layer of material whichis applied over an underlying layer of material, and patternedto have openings, so that the underlying layer can beprocessed where there are openings. After processing theunderlying layer, the mask may be removed. Commonmasking materials are photoresist (resist) and nitride. Nitrideis usually considered to be a “hard mask.”metalli-Metallization refers to formation of metal contacts andzationinterconnects in the manufacturing of semiconductordevices. This generally occurs after the devices arecompletely formed, and ready to be connected with oneanother. A first level or layer of metallization is usuallyreferred to as “M1.”nitridecommonly used to refer to silicon nitride (chemical formulaSi3N4). A dielectric material commonly used in integratedcircuit manufacturing. Forms an excellent mask (barrier)against oxidation of silicon (Si). Nitride iscommonly used as a hard mask (HM).n-typesemiconductor in which concentration of electrons is higherthan the concentration of “holes”. See p-type.oxidecommonly used to refer to silicon dioxide (SiO2). Alsoknown as silica. SiO2 is the most common insulator insemiconductor device technology, particularly in siliconMOS/CMOS where it is used as a gate dielectric (gateoxide); high quality films are obtained by thermal oxidationof silicon. Thermal SiO2 forms a smooth, low-defectinterface with Si, and can be also readily deposited by CVD.Oxide may also be used to fill STI trenches, form spacerstructures, and as an inter-level dielectric, for example.plasma Plasma etching refers to dry etching in which semiconductoretchingwafer is immersed in plasma containing etching species;chemical etching reaction is taking place at the same rate inany direction, i.e. etching is isotropic; can be very selective;used in those applications in which directionality(anisotropy) of etching in not required, e.g. in resiststripping.polyshort for polycrystalline silicon (Si). Heavily doped poly Siis commonly used as a gate contact in silicon MOS andCMOS devices;p-typesemiconductor in which concentration of “holes” is higherthan the concentration of electrons. See n-type. Examples ofp-type silicon include silicon doped (enhanced) with boron(B), Indium (In) and the like.resistshort for photoresist. also abbreviated “PR”. Photoresist isoften used as a masking material in photolithographicprocesses to reproduce either a positive or a negative imageon a structure, prior to etching (removal of material which isnot masked). PR is usually washed off after having servedits purpose as a masking material.RIEshort for Reactive Ion Etching. RIE is a variation of plasmaetching in which during etching, the semiconductor wafer isplaced on an RF powered electrode. The plasma is generatedunder low pressure (vacuum) by an electromagnetic field. Ituses chemically reactive plasma to remove materialdeposited on wafers. High-energy ions from the plasmaattack the wafer surface and react with it. The wafer takes onpotential which accelerates etching species extracted fromplasma toward the etched surface. A chemical etchingreaction is preferentially taking place in the direction normalto the surface—in other words, etching is more anisotropicthan in plasma etching but is less selective. RIE typicallyleaves the etched surface damaged. RIE is a very commonetching mode in semiconductor manufacturing.Self-AlignAs used herein “self-align” means that specific surfaces ofthe metallized (silicided) bottom electrode extendcontrollable distances into the silicon substrate in the deeptrench. An inherent advantage of a self aligned fabricationprocess according to the present invention is that themetallized bottom electrode is not formed in undesirablelocations of the capacitor such as in the vertical walls of theburied oxide (BOX) and the silicon (SOI).SiSilicon, a semiconductor.SI unitsThe International System of Units (abbreviated SI from theFrench Le Système international d'unités) is the modernform of the metric system and is generally a system devisedaround the convenience of the number 10. It is the world'smost widely used system of units, both in everydaycommerce and in science. The SI system of units consists ofa set of units together with a set of prefixes. There are seven“base units”, which are meter (abbreviated “m”, for length),kilogram (abbreviated “kg”, for mass), second (abbreviated“s”, for time), Ampere (abbreviated “A”, for electriccurrent), Kelvin (abbreviated “K”, for thermodynamictemperature), mole (abbreviated “mol”, for the amount of asubstance) and candela (abbreviated “cd”, for luminousintensity). A prefix may be added to the units to produce amultiple of the original unit. All multiples are integerpowers of ten. For example, “kilo” denotes a multiple of athousand and “milli” denotes a multiple of one-thousandth.Hence there are one thousand millimeters to the meter andone thousand meters to the kilometer.SOIshort for silicon-on-insulator. Silicon on insulator (SOI)technology refers to the use of a layeredsilicon-insulator-silicon substrate in place of a conventionalsilicon substrate in semiconductor manufacturing, especiallymicroelectronics, SOI-based devices differ fromconventional silicon-built devices in that the silicon junctionis above an electrical insulator, typically silicon dioxide or(less commonly) sapphire.STIshort for shallow trench isolation. Generally, a trench etchedinto the substrate and filled with an insulating material suchas oxide, to isolate one region of the substrate from anadjacent region of the substrate. One or more transistors ofa given polarity may be disposed within an area isolated bySTI.substratetypically a wafer, of semiconductor material such as silicon,germanium, silicon germanium, silicon carbide, and thoseconsisting essentially of III-V compound semiconductorssuch as GaAs, II-VI compound semiconductors such asZnSe. A substrate may also comprise an organicsemiconductor or a layered semiconductor such as, forexample, Si/SiGe, a silicon-on-insulator or aSiGe-on-insulator. A portion or entire semiconductorsubstrate may be amorphous, polycrystalline, ormonocrystalline. A substrate is often covered by an oxidelayer (sometimes referred to as a “pad oxide layer”). Padoxide is usually relatively thin, e.g., in the range of about 50to about 500 Angstroms (5-50 nm), and can be formed, forexample, by thermal oxidation of the substrate. Pad oxidemay also be prepared by other methods. For example, silicondioxide or reactive precursors like silane could be depositedby chemical vapor deposition (CVD). A nitride layer(sometimes referred to as a “pad nitride layer”) may beformed to protect the pad oxide and the underlying substrateduring various processing steps. It usually has a thickness inthe range of about 100 Angstroms to about 6000 Angstroms(10-600 nm), such as in the range of about 1500 Angstromsto about 3000 Angstroms (150-300 nm). Conventionalmeans can be used to apply the pad nitride, such as chemicalvapor deposition (CVD).transistorA transistor is a semiconductor device, commonly used as anamplifier or an electrically controlled switch. The transistoris the fundamental building block of the circuitry incomputers, cellular phones, and all other modern electronicdevices. Because of its fast response and accuracy, tiletransistor is used in a wide variety of digital and analogfunctions, including amplification, switching, voltageregulation, signal modulation, and oscillators. Transistorsmay be packaged individually or as part of an integratedcircuit, some with over a billion transistors in a very smallarea. See FET.Units of Various units of length may be used herein, as follows:Lengthmeter (m)A meter is the SI unit of length, slightly longer thana yard. 1 meter = ~39 inches. 1 kilometer (km) =1000 meters = ~0.6 miles.1,000,000 microns = 1 meter. 1,000 millimeters(mm) = 1 meter.100 centimeters (cm) = 1 meter.micron (μm)one millionth of a meter (0.000001 meter); alsoreferred to as a micrometer.mil 1/1000 or 0.001 of an inch; 1 mil = 25.4 microns.nanometerone billionth of a meter (0.000000001 meter).(nm)Angstrom({acute over (Å)}) one tenth of a billionth of a meter. 10 {acute over (Å)} = 1 nm.Vshort for voltage. Different voltages may be applied todifferent parts of a transistor or memory cell to control itsoperation.waferIn microelectronics, a wafer is a thin slice of semiconductingmaterial, such as a silicon crystal, upon which microcircuitsare constructed. There are multiple orientation planes in thesilicon crystal that can be used. The planes are defined by the“Miller Indices” methodology. Common orientationsclassified by the “Miller indices” are (100), (011), (110), and(111).work The work function is the minimum energy (usually measuredfunctionin electron volts) needed to remove an electron from a solidto a point immediately outside the solid surface (or energyneeded to move an electron from the Fermi energy level intovacuum). Here “immediately” means that the final electronposition is far from the surface on the atomic scale but stillclose to the solid on the macroscopic scale. The workfunction is an important property of metals. The magnitudeof the work function is usually about a half of the ionizationenergy of a free atom of the metal.